8731-01 Datasheet, PDF (1/17 Pages) Integrated Device Technology – Differential reference clock input pair

Low SKEW, 1-to-11 Differential-to-3.3V
LVPECL Clock Multiplier / Zero Delay Buffer
8731-01
DATA SHEET
GENERAL DESCRIPTION
The 8731-01 is a low voltage, low skew,
1-to-11 Differential-to-3.3V LVPECL Clock Multiplier/Zero
Delay Buffer . With output frequencies up to 700MHz
the 8731-01 is targeted at high performance clock
applications. Along with a fully integrated PLL the 8731-
01 contains frequency configurable, differential out-
puts and external feedback inputs for multiplying clock
frequencies and regenerating clocks with “zero delay”.
Frequency multiplication is achieved by utilizing the
separate feedback and clock output dividers. The value
of the multiplier is determined by the ratio of the feedback
divider, M, to the output divider,N. For multiplier values greater
than 1, M must be greater than N. For multiplier values less
than 1,M must be less than N. The zero delay mode is achieved
with M and N at equal values. The divide values of the clock
and feedback outputs are controlled by the DIV_SEL0:2 and
FB_SEL0:1 inputs, respectively. The 8731-01 accepts any
differential signal and translates it to differential 3.3V LVPECL
output levels.
FEATURES
• Eleven differential 3.3V LVPECL outputs
• Differential reference clock input pair
• REF_CLK, nREF_CLK pair can accept the following differ-
ential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Maximum reference clock input frequency: 200MHz
• VCO range: 250MHz - 700MHz
• Accepts any single-ended input signal with a resistor bias
on nCLK input
• External feedback for zero delay capabilitiy
• Output skew: 70ps (maximum)
• Cycle-to-cycle jitter: 65ps (maximum)
• Full 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM
PIN ASSIGNMENT
8731-01 REVISION B 7/14/15
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
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