871002AGI-02LF Datasheet, PDF (1/16 Pages) Integrated Device Technology – Differential-to-0.7V HCSL Differential PCI EXPRESS™ Jitter Attenuator

Differential-to-0.7V HCSL Differential
PCI EXPRESS™ Jitter Attenuator
ICS871002I-02
DATA SHEET
General Description
The ICS871002I-02 is a high performance Jitter
ICS
Attenuator designed for use in PCI Express™systems.
HiPerClockS™ _{In some PCI Express systems, such as those found in}
desktop PCs, the PCI Express clocks are generated
from a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS871002I-02 has two PLL bandwidth modes: 350kHz and
2200kHz. The 350kHz mode provides the maximum jitter
attenuation, but it also results in higher PLL tracking time. In this
mode, the spread spectrum modulation may also be attenuated. The
2200kHz bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be as good as
the lower bandwidth modes. The ICS871002I-02 can be set for
different modes using the F_SELx pins as shown in Table 3C.
The ICS871002I-02 uses IDT 3^rd Generation FemtoClock^TM PLL
technology to achieve the lowest possible phase noise. The
device is packaged in a small 20 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
Features
• Two 0.7V HCSL differential output pairs
• One differential clock input
• CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
• Input frequency range: 98MHz to 128MHz
• Output frequency range: 98MHz to 640MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 45ps (maximum)
• Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
PLL Bandwidth (typical) Table
BW_SEL
0 = PLL Bandwidth: ~350kHz (default)
1 = PLL Bandwidth: ~2200kHz
Block Diagram
Pin Assignment
nQ0 1
IREF 2
FB_OUT 3
nFB_OUT 4
MR 5
BW_SEL 6
F_SEL1 7
VDDA 8
F_SEL0 9
VDD 10
20 Q0
19 VDD
18 Q1
17 nQ1
16 nFB_IN
15 FB_IN
14 GND
13 nCLK
12 CLK
11 OE
ICS871002I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS871002AGI-02 REVISION A APRIL 14, 2010
IREF
OE ^Pullup
F_SEL[1:0] ^{Pullup:Pulldown 2}
BW_SEL ^Pulldown
0 = 350kHz
1 = 2200kHz
CLK ^Pulldown
nCLK ^Pullup
Phase
Detector
FB_IN ^Pulldown
nFB_IN ^Pullup
MR ^Pulldown
1
VCO
490 - 640 MHz
Output Divider
00 ÷5
01 ÷4
10 ÷2 (default)
11 ÷1
÷5 (fixed)
Q0
nQ0
Q1
nQ1
FB_OUT
nFB_OU
©2010 Integrated Device Technology, Inc.