8705I Datasheet, PDF (1/18 Pages) Integrated Device Technology – Output frequency range

Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
Not Recommend for New Designs
8705I
DATA SHEET
GENERAL DESCRIPTION
The 8705I is a highly versatile 1:8 Differential-to-LVCMOS/
LVTTL Clock Generator. The 8705I has two selectable clock
inputs. The CLK1, nCLK1 pair can accept most standard
differential input levels. The single ended CLK0 input accepts
LVCMOS or LVTTL input levels.The 8705I has a fully integrated
PLL and can be configured as zero delay buffer, multiplier
or divider and has an input and output frequency range of
15.625MHz to 250MHz. The reference divider, feedback divider
and output divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8.The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
FEATURES
• Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
• Not Recommended for New Designs
For new designs, contact IDT.
BLOCK DIAGRAM
PIN ASSIGNMENT
8705I REVISION E 7/13/15
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
1
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