87016I Datasheet, PDF (1/17 Pages) Integrated Device Technology – Maximum output frequency

Low Skew, 1-to-16 LVCMOS/LVTTL Clock
Generator
87016I
DATA SHEET
Description
The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator.
The device has four banks of four outputs and each bank can be
independently selected for 1 or 2 frequency operation. Each bank
also has its own power supply pins so that the banks can operate at
the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low
impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the output
frequency of each bank. The output banks can be independently
selected for 1 or 2 operation. The bank enable inputs,
CLK_ENA:CLK_END, support enabling and disabling each bank of
outputs individually. The CLK_ENA:CLK_END circuitry has a
synchronizer to prevent runt pulses when enabling or disabling the
clock outputs. The master reset input, MR/OE, resets the 1/2 flip
flops and also controls the active and high impedance states of all
outputs. This pin has an internal pull-up resistor and is normally used
only for test purposes or in systems which use low power modes.
The 87016I is characterized to operate with the core at 3.3V or 2.5V
and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and
part-to-part skew characteristics make the 87016I ideal for those
clock applications demanding well-defined performance and
repeatability.
Features
• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input
• CLK1, CLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V
operation
• Asynchronous clock enable/disable
• Output skew: 170ps (maximum)
• Bank skew: 50ps (maximum
• Part-to-Part Skew: 800ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Lead-free packaging
Block Diagram
MR/OE
CLK0
CLK1
CLK1
CLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
0
÷1
1
1
÷2
0
1
0
1
0
1
0
Pin Assignment
D
LE
4
QA0:QA3
D
LE
4
QB0:QB3
D
LE
4
QC0:QC3
D
LE
4
QD0:QD3
VDD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
MR/OE
GND
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
GND
QB0
VDDOB
QB1
GND
QB2
VDDOB
QB3
GND
QC0
VDDOC
QC1
87016I
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
87016I Rev C 3/23/15
1
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