86004I Datasheet, PDF (1/13 Pages) Integrated Device Technology – CLK accepts the following input levels

15.625MHZ to 62.5MHZ, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
86004I
DATA SHEET
GENERAL DESCRIPTION
The 86004I is a high performance 1:4 LVCMOS/LVTTL Clock Buffer.
The 86004I has a fully integrated PLL and can be configured as
zero delay buffer and has an input and output frequency range of
15.625MHz to 62.5MHz. The VCO operates at a frequency range
of 250MHz to 500MHz. The external feedback allows the device to
achieve “zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system test
and debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output divider.
FEATURES
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 15.625MHz to 62.5MHz
• Input frequency range: 15.625MHz to 62.5MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter: 75ps (maximum)
• Output skew: 65ps (maximum)
• Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply
• -40°C to 85° ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM
PIN ASSIGNMENT
86004I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
86004I REVISION A 7/10/15
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