854S057B_16 Datasheet, PDF (1/15 Pages) Integrated Device Technology – 4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
854S057B
Datasheet
General Description
The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can
operate up to 2GHz. The PCLK, nPCLK pairs can accept most
standard differential input levels. Internal termination is provided on
each differential input pair. The 854S057B operates using a 2.5V
supply voltage. The fully differential architecture and low propagation
delay make it ideal for use in high speed multiplexing applications.
The select pins have internal pulldown resistors. Leaving one input
unconnected (pulled to logic low by the internal resistor) will
transform the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins will
select the same numbered data input (i.e., 00 selects PCLK0,
nPCLK0).
Features
• High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
• One LVDS output pair
• Four selectable PCLK, nPCLK inputs with internal termination
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 800ps (maximum)
• Additive phase jitter, RMS: 0.065ps (typical)
• Full 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
VT0
50
50
PCLK0
nPCLK0
VT1
50
50
PCLK1
nPCLK1
VT2
50
50
PCLK2
nPCLK2
VT3
00
01
Q
10
nQ
11
50
50
PCLK3
nPCLK3
SEL1 Pulldown
SEL0 ^Pulldown
©2016 Integrated Device Technology, Inc.
Pin Assignment
VDD 1
PCLK0 2
VT0 3
nPCLK0 4
SEL1 5
SEL0 6
PCLK1 7
VT1 8
nPCLK1 9
GND 10
20 VDD
19 PCLK3
18 VT3
17 nPCLK3
16 Q
15 nQ
14 PCLK2
13 VT2
12 nPCLK2
11 GND
854S057B
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
1
Revision B, February 10, 2016