854S006I Datasheet, PDF (1/15 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to- LVDS Fanout Buffer

Low Skew, 1-to-6, Differential-to-
LVDS Fanout Buffer
854S006I
Data Sheet
GENERAL DESCRIPTION
The 854S006I is a low skew, high perfor- mance 1-to-6 Differen-
tial-to-LVDS Fanout Buffer. The CLK, nCLK pair can accept most
standard differential input levels. The 854S006I is characterized
to operate from either a 2.5V or a 3.3V power supply. Guaranteed
output skew characteristics make the 854S006I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
FEATURES
• Six differential LVDS outputs
• One differential clock input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 1.7GHz
• Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
• Output skew: 55ps (maximum)
• Propagation delay: 850ps (maximum)
• Additive phase jitter, RMS: 0.067ps (typical)
• Full 3.3V or 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
BLOCK DIAGRAM
CLK ^Pullup
nCLK ^Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
PIN ASSIGNMENT
nCLK ₁
CLK ₂
VDD 3
VDDO 4
Q0 5
nQ0 ⁶
GND 7
Q1 8
nQ1 9
VDDO 10
Q2 11
nQ2 ¹²
24 ^GND
23 GND
22 ^VDD
21 ^VDDO
20 nQ5
19 Q5
18 GND
17 nQ4
16 _Q4
15 _VDDO
14 nQ3
13 _Q3
854S006I
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B January 19, 2016