854S006 Datasheet, PDF (1/17 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to-LVDS Fanout Buffer

Low Skew, 1-to-6,
Differential-to-LVDS Fanout Buffer
854S006
Datasheet
Description
The 854S006 is a low skew, high performance 1-to-6,
Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept
most standard differential input levels. The 854S006 is
characterized to operate from either a 2.5V or a 3.3V power
supply. Guaranteed output and part-to-part skew characteristics
make the 854S006 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
▪ Six differential LVDS outputs
▪ One differential clock input pair
▪ CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
▪ Maximum output frequency: 1.7GHz
▪ Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
▪ Output Skew: 55ps (maximum)
▪ Propagation delay: 850ps (maximum)
▪ Additive phase jitter, RMS: 0.067ps (typical)
▪ Full 3.3V or 2.5V supply
▪ -40°C to 85°C ambient operating temperature
▪ Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
CLK
nCLK
Pull-up
Pull-down
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Pin Assignment
nCLK 1
CLK 2
VDD
3
VDDO
4
Q0 5
nQ0 6
GND 7
Q1 8
nQ1 9
VDDO
10
Q2 11
nQ2 12
24 GND
23 GND
22
VDD
21
VDDO
20 nQ5
19 Q5
18 GND
17 nQ4
16 Q4
15
VDDO
14 nQ3
13 Q3
©2017 Integrated Device Technology, Inc.
1
April 11, 2017