853S54I-01 Datasheet, PDF (1/20 Pages) Integrated Device Technology – Dual 2:1, 1:2 Differential-to-LVPECL/ ECL Multiplexer

Dual 2:1, 1:2 Differential-to-LVPECL/
ECL Multiplexer
853S54I-01
Datasheet
General Description
The 853S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device
may be useful for multiplexing multi-rate Ethernet PHYs which
have 100Mbit and 1000Mbit transmit/receive pairs onto an optical
SFP module which has a single transmit/receive pair. A 3^RD mode
allows loop back testing and allows the output of a PHY transmit
pair to be routed to the PHY input pair. For examples, please refer
to the Application Block diagrams on pages 2-3 of the data sheet.
The 853S54I-01 is optimized for applications requiring very high
performance and has a maximum operating frequency in 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
• Dual 2:1, 1:2 MUX
• Three LVPECL output pairs
• Three differential clock inputs can accept: LVPECL, LVDS, CML
• Loopback test mode available
• Maximum output frequency: 2.5GHz
• Propagation delay: 550ps (maximum)
• Part-to-part skew: 275ps (maximum)
• Additive phase jitter, RMS: 27fs (typical)
• LVPECL mode operating voltage supply range:
V_CC = 2.375V to 3.465V, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
INB ^Pulldown
nINB ^{Pullup/Pulldown}
0
QB
nQB
1
SELB
0
1
Pin Assignment
Pulldown
INA0
Pullup/Pulldown _nINA0
LOOP 0
QA0
nQA0
Pulldown
INA1
Pullup/Pulldown _nINA1
LOOP 1
QA1
nQA1
16 15 14 13
QA0 1
12 INA0
nQA0 2
11 nINA0
QA1 3
10 INA1
nQA1 4
9 nINA1
5 6 78
853S54I-01
16-Lead VFQFN
3mm x 3mm x 0.925mm
package body
K Package
Top View
SELA
©2017 Integrated Device Technology, Inc.
1
March 2, 2017