8530I-01_15 Datasheet, PDF (1/18 Pages) Integrated Device Technology – Low Skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer

Low Skew, 1-to-16 Differential-to-3.3V
LVPECL Fanout Buffer
8530I-01
Datasheet
General Description
The 8530I-01is a low skew, 1-to-16 Differential- to-3.3V LVPECL
Fanout Buffer. The CLK, nCLK pair can accept most standard
differential input levels. The high gain differential amplifier accepts
peak-to-peak input voltages as small as 150mV as long as the
common mode voltage is within the specified minimum and
maximum range.
Guaranteed output and part-to-part skew characteristics make the
8530I-01 ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
• Sixteen differential 3.3V LVPECL output pairs
• CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with a resistor bias on nCLK input
• Output skew: 75ps (maximum)
• Additive phase jitter, RMS @ 106.25MHz: 0.162ps (typical)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK0 ^Pulldown
nCLK0 ^Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
©2015 Integrated Device Technology, Inc.
Pin Assignment
VCCO
Q11
nQ11
Q10
nQ10
VEE
Q9
nQ9
Q8
nQ8
VCCO
VCC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
CLK
VCCO
nQ0
Q0
nQ1
Q1
VEE
nQ2
Q2
nQ3
Q3
VCCO
8530I-01
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
1
Revision B, December 1, 2015