85304AG-01LFT Datasheet, PDF (1/15 Pages) Integrated Device Technology – Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

Low Skew, 1-to-5, Differential-to-3.3V
LVPECL Fanout Buffer
ICS85304-01
DATA SHEET
General Description
The ICS85304-01 is a low skew, high performance 1-to-5
Differential-to-3.3V LVPECL fanout buffer. The ICS85304-01 has two
selectable clock inputs. The CLKx, nCLKx pairs can accept most
standard differential input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs during
asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS85304-01 ideal for those applications demanding well defined
performance and repeatability.
Features
• Five 3.3V differential LVPECL output pairs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx input pairs can accept the following differential
levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx inputs
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.1ns (maximum)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
Block Diagram
CLK_EN ^Pullup
CLK0 ^Pulldown
nCLK0 ^Pullup
00
CLK1 ^Pulldown
nCLK1 ^Pullup
1¹
CLK_SEL ^Pulldown
D
Q
LE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Pin Assignment
Q0 1
nQ0 2
Q1 3
nQ1 4
Q2 5
nQ2 6
Q3 7
nQ3 8
Q4 9
nQ4 10
20 VCC
19 CLK_EN
18 VCC
17 nCLK1
16 CLK1
15 VEE
14 nCLK0
13 CLK0
12 CLK_SEL
11 VCC
ICS85304-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS843N001BGI REVISION E DECEMBER 19, 2012
1
©2012 Integrated Device Technology, Inc.