79RC64574 Datasheet, PDF (1/28 Pages) Integrated Device Technology – Advanced 64-bit Microprocessors Product Family

Advanced 64-bit
Microprocessors
Product Family
79RC64574^™
79RC64575^™
Features
◆ _{High-performance 64-bit embedded Microprocessor}
– 250MHz operating frequency
– >330 Dhrystone MIPS performance
– 300MFLOPS/s floating-point performance
– Up to 125 million multiply accumulate per second (MAC/s)
– MIPS-IV Instruction Set Architecture (ISA), with integer DSP
and 3-operand integer multiply extensions
– Limited dual-issue microarchitecture
◆ _{Compatible with RC4640 and RC32364 DSP extensions}
– DSP Extensions, for consumer applications
– 2-cycle repeat rate, on atomic Multiply-add
– Multiply-subtract (MSUB) support, for complex number
processing
– Count-leading-zero/one support, for string searches and
normalization
◆ _{High-performance on-chip cache subsystem}
– 32kB, two-set associative instruction cache (I-cache)
– 32kB, two-set associative data cache (D-cache)
– Write-through and write-back data cache operations
– High-performance cache-ops, bandwidth management
◆ _{I-cache and D-cache locking capability (per line), provides}
improved real-time support
◆ _{Joint TLB on-chip, for virtual-to-physical address mapping}
◆ _{Big- or Little-endian capability}
◆ _{RC5000 compatible memory management}
– On-chip 48-entry, 96-page TLB, for advanced operating
system support
– Compatible with major operating systems:
Windows^®CE, VxWorks, and others
◆ _{Bus compatible with IDT 64-bit microprocessor families}
– Pipeline runs at 2 to 8 times the bus frequency
– Bus speeds to 125MHz
– 32-bit bus option, for lower cost systems
– Enhanced timing protocol for SyncDRAM systems (compatible
with IDT79RC64474/475)
◆ _RC64574:
– 32-bit SysAd bus, for low-cost systems
– Pin compatible with RC4640 and RC64474
– 128-pin QFP package
◆ _RC64575:
– 64-bit SysAd bus interface
– Pin compatible with RC4650 and RC64475
– 208-pin QFP package
◆ _{Industrial temperature range support}
◆ _{JTAG Boundary Scan Interface}
◆ _{2.5V operation with 3.3V tolerant I/O}
Block Diagram
PLL
64-bit
Integer
Execution Unit
DSP
Accelerator
666 MFIOPS
IEEE 1284
Floating-Point
Accelerator
Dual-Issue Instruction Fetch Unit
Primary Cache Controller
32kB
2 set-associative
Instruction
Cache
(Lockable)
32kB
2 set-associative
Data
Cache
(Lockable)
RC5000
Compatible
System Control
Coprocessor
48-entry
96-page
TLB
64-bit/32-bit
RC64474/475 Compatible
System Interface
ClkIn
Figure 1 RC64574/RC64575 Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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© 2001 Integrated Device Technology, Inc.
December 14, 2001
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