79RC5000 Datasheet, PDF (1/15 Pages) Integrated Device Technology – MULTI-ISSUE 64-BIT MICROPROCESSOR

MULTI-ISSUE
64-BIT MICROPROCESSOR
79RC5000
)HDWXUHV
x _{Dual issue super-scalar execution core}
– 250 MHz frequency
– Dual issue floating-point ALU operations with other instruction
classes
– Traditional 5-stage pipeline, minimizes load and branch laten-
cies
x _{Single-cycle repeat rate for most floating point ALU}
operations
x _{High level of performance for a variety of applications}
– High-performance 64-bit integer unit achieves 330 dhrystone
MIPS (dhrystone 2.1)
– Ultra high-performance floating-point accelerator, directly
implementing single- and double-precision operations
achieves 500mflops
– Extremely large on-chip primary cache
– On-chip secondary cache controller
x _{MIPS-IV 64-bit ISA for improved computation}
– Compound floating-point operations for 3D graphics and
floating-point DSP
– Conditional move operations
x _{Large on-chip TLB}
x _{Active power management, including use of WAIT operation}
x _{Large, efficient on-chip caches}
– 32KB Instruction Cache, 32KB Data Cache
– 2-set associative in each cach
– Virtually indexed and physically tagged to minimize cache
flushes
– Write-back and write-through selectable on a per page basis
– Critical word first cache miss processing
– Supports back-to-back loads and stores in any combination at
full pipeline rate
x _{High-performance memory system}
– Large primary caches integrated on-chip
– Secondary cache control interface on-chip
– High-frequency 64-bit bus interface runs up to 125MHz
– Aggregate bandwidth of on-chip caches, system interface of
5.6GB/s
– High-performance write protocols for graphics and data
communications
x _{Compatible with a variety of operating systems}
– Windows™ CE
– Numerous MIPS-compatible real-time operating systems
x _{Uses input system clock, with processor pipeline clock}
multiplied by a factor of 2-8
x _{Industrial and commercial temperature range}
%ORFN 'LDJUDP
Data Set A
Store Buffer
Control
W rite Buffer
Read Buffer
Data Set B
DBus
Floating Point Register File
Unpacker/Packer
Floating Point
M Add,Add,Sub, Cvt
Div, SqRt
SysAD
Phase Lock Loop
Data Tag A
DTLB Physical
FPIBus
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Tag
A u x Ta g
Joint TLB
Coprocessor 0
System/M emory
C o n tro l
D VA
IVA
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
Instruction Set A
Instruction Select
Integer Instruction Register
FP Instruction Register
Instruction Set B
IntIBus
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
ABus
Integer M ultiply, Divide
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
 2001 Integrated Device Technology, Inc.
1 of 15
April 10, 2001
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