79RC32364 Datasheet, PDF (1/21 Pages) Integrated Device Technology – RISController Embedded 32-bit Microprocessor, based on RISCore32300

RISController^TM Embedded 32-bit
Microprocessor, based on
RISCore32300
79RC32364^™
Features
x _{High-performance embedded RISController}TM
microprocessor, based on IDT RISCore32300^TM 32-bit CPU
core
– Based on MIPS 32 RISC architecture with enhancements
– Scalar 5-stage pipeline minimizes branch and load delays
– 66 Million multiply accumulate (MAC) Mul-Add/second
@ 133MHz
– 100 and 133 frequencies
x _{MIPS 32 (ISA) instruction set architecture}
– MIPS IV compatible conditional move instructions
– MIPS IV superset PREF (prefetch) instruction
– Fast multiplier with atomic multiply-add, multiply-sub
– Count leading zeros/ones instructions
x _{Large, efficient on-chip caches}
– Separate 8kB Instruction cache and 2kB Data cache
– 2-way set associative
– Write-back and write-through support on a per page basis
– Optional cache locking with “per line” resolution, to facilitate
deterministic response
– Simultaneous instruction and data fetch in each clock cycle,
sustained rate, achieves over 1 GB/sec bandwidth
x _{Flexible RC4000 compatible MMU with 32-page TLB on-chip}
– Variable page size
– Variable number of locked entries
– No performance penalty for address translation
x _{Flexible bus interface allows simple, low-cost designs}
– Bus interface runs at a fraction of pipeline rate
– Programmable port-width interface (8-,16-, 32-bit memory and
I/O regions)
– Programmable bus turnaround times (BTA)
– Supports single data or burst transactions
x _{Improved real-time support}
– Fast interrupt decode
x _{Low-power operation}
– Active power management: powers down inactive units
– Typical power 700mW @ 133MHz
– Stand-by mode <300mW
x _{Enhanced JTAG interface, for low-cost in-circuit emulation}
(ICE)
x _{MIPS architecture ensures applications software}
compatibility throughout the RISController series of
embedded processors
x _{Industrial temperature range support}
x _{3.3V operation (core and I/O)}
Block Diagram
RISCore32300^TM
Extended MIPS 32
Integer CPU Core
MMU ^{RISCore4000 Compatible}
w/ ^{System Control}
TLB Coprocessor (CPO)
8kB I-Cache,
2-set, lockable
2kB D-Cache, 2-set,
lockable, write-back/write-through
Clock
Generation
Unit
RISCore32300 Internal Bus Interface
RC32364 Bus Interface Unit
The IDT logo is a registered trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
 2000 Integrated Device Technology, Inc.
1 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
DSC 4510