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79RC32355 Datasheet, PDF (1/47 Pages) Integrated Device Technology – Communications Processor | |||
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IDTTM InterpriseTM Integrated
Communications Processor
79RC32355
Features List
â RC32300 32-bit Microprocessor
â Enhanced MIPS-II ISA
â Enhanced MIPS-IV cache prefetch instruction
â DSP Instructions
â MMU with 16-entry TLB
â 8KB Instruction Cache, 2-way set associative
â 2KB Data Cache, 2-way set associative
â Per line cache locking
â Write-through and write-back cache management
â Debug interface through the EJTAG port
â Big or Little endian support
â Interrupt Controller
â Allows status of each interrupt to be read and masked
â I2C
â Flexible I2C standard serial interface to connect to a variety of
peripherals
â Standard and fast mode timing support
â Configurable 7 or 10-bit addressable slave
â UARTs
â Two 16550 Compatible UARTs
â Baud rate support up to 1.5 Mb/s
â Counter/Timers
â Three general purpose 32-bit counter/timers
â General Purpose I/O Pins (GPIOP)
â 36 individually programmable pins
â Each pin programmable as input, output, or alternate function
â Input can be an interrupt or NMI source
â Input can also be active high or active low
Block Diagram
â SDRAM Controller
â 2 memory banks, non-interleaved, 512 MB total
â 32-bit wide data path
â Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
â SODIMM support
â Stays on page between transfers
â Automatic refresh generation
â Peripheral Device Controller
â 26-bit address bus
â 32-bit data bus with variable width support of 8-,16-, or 32-bits
â 8-bit boot ROM support
â 6 banks available, up to 64MB per bank
â Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
â Supports external wait-state generation, Intel or Motorola style
â Write protect capability
â Direct control of optional external data transceivers
â System Integrity
â Programmable system watchdog timer resets system on time-
out
â Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
â DMA
â 16 DMA channels
â Services on-chip and external peripherals
â Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
â Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
â Supports unaligned transfers
â Supports burst transfers
RC32300
CPU Core
ICE
EJTAG MMU
D. Cache I. Cache
Interrupt
:
Controller :
3 Counter
Timers
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
I2C
Controller
2 UARTS
(16550)
GPIO
Interface
TDM
Interface
ATM
Interface
Memory & I2C Bus
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins TDM Bus
Figure 1 RC32355 Internal Block Diagram
Utopia 1 / 2
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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May 25, 2004
DSC 5900
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