79RC32334 Datasheet, PDF (1/30 Pages) Integrated Device Technology – IDT Interprise Integrated Communications Processor

IDT^TM Interprise^TM Integrated
Communications Processor
79RC32334—Rev. Y
Features
◆ _{RC32300 32-bit Microprocessor}
– Up to 150 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
– Supports big or little endian operation
– MMU with 32 page TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
◆ _{Local Bus Interface}
– Up to 75 MHz operation
– 26-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
◆ _{Interrupt Controller simplifies exception management}
◆ _{Four general purpose 32-bit timer/counters}
Block Diagram
◆ _{Programmable I/O (PIO)}
– Input/Output/Interrupt source
– Individually programmable
◆ _{SDRAM Controller (32-bit memory only)}
– 4 banks, non-interleaved
– Up to 512MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 512Mb SDRAM device depths
– Automatic refresh generation
◆ _{Serial Peripheral Interface (SPI) master mode interface}
◆ _{UART Interface}
– Two 16550 compatible UARTs
– Baud rate support up to 1.5 Mb/s
– Modem control signals available on one channel
◆ _{Memory & Peripheral Controller}
– 6 banks, up to 64MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
EJTAG
In-Circuit Emulator Interface
RISCore32300
RC5000
Enhanced MIPS-II ISA Compatible
Integer CPU
CP0
32-page
TLB
2kB
2-set, Lockable
Data Cache
8kB
2-set
Lockable
Instr. Cache
IPBus
Bridge
Interrupt Control
32-bit Timers
DMA Control
Dual UART
IDT
Peripheral
Bus
Programmable I/O
SPI Control
Local
Memory/IO
Control
SDRAM
Control
PCI Bridge
Figure 1 RC32334 Block Diagram
Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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August 31, 2004
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