70K2000 Datasheet, PDF (1/2 Pages) Integrated Device Technology – Serial RapidIO Pre-Processing Switch for DSP Clusters

Serial RapidIO^TM
Pre-Processing Switch
for DSP Clusters
Product Brief
70K2000
Device Overview
The IDT70K2000 is a serial RapidIO^TM Pre-Processing Switch (PPS). The
PPS is central to the "DSP Farms" processing architecture. It may also be used
in serial RapidIO backplane switching. The PPS performs a variety of data
processing on the payload of sample packets to accelerate the subsequent algo-
rithmic operations of a receiving processor (DSP, CRP, FPGA). It supports serial
RapidIO^TM packet switching (unicast, multicast, or broadcast) from any input to
any output port. The PPS accelerates baseband processing in support of a
variety of wireless standards. It may also be used for video imaging such as that
in medical equipment, high-end surveillance, or similar signal processing-inten-
sive applications.
Features
◆ _{Interfaces - sRIO}
– 40 bidirectional serial RapidIO (sRIO) lanes v 1.3
– Port Speeds selectable; 3.125Gbps, 2.5Gbps, or 1.25Gbps
– Short haul or long haul reach for each PHY speed
– Configurable in up to 22 ports (1x and 4x link implementations)
– Error management supports standard and enhanced port operations
◆ _{Interfaces - I}2_C
– One I²C port for maintenance and error reporting
◆ _Switch
– 10Gbps peak throughput
◆ _{Packet Processor}
– 100Gbps peak throughput
– 10 Individual Packet Processing Scenarios (PPSc), each capable of:
Within Sample Processing
– Sign Extension/Deletion, Endian Change
– Programmable number of bits per sample 2B; 4<=B<=32 bits
– Sample Format; I/Q format or I only
Within Packet Processing
– Any sample can be extracted from any 256 locations of any of 22
incoming sample packets
– The chosen sample can be placed into any location of the resultant
packet (up to 256 locations)
– Up to 22 samples can be summed to give one sample ouput, which
is placed in any location of resultant packet
– Multiple packets can be generated from a single PPSc going to a
single port
– Up to 8 packets can be created by a single PPSc
– Each packet can be assigned a specific 32-bit memory address (in
sRIO header)
– Multiple packets from a group of input sample packets can be gener-
ated by concurrently using multiple PPSc
– SWRITE packets formed for Packet Processor Output Packets
– Incoming packet header information will be used in the resultant
packet
Summation of up to 22 packets
– 37 bit summing of each I or Q sub-sample
– Dynamic Range or saturation of Result to 4-32 bit range
– 8 Group Scenarios each of which can address up to 4 Individual
PPSc
◆ _{Synchronization}
– Non-TDM sychronization of packets from multiple ports
◆ _{Package: 676-ball grid array, 27mm x 27mm, 1.0mm ball pitch}
Block Diagram
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February 13, 2006
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is
subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual
power of acceptance.
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