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5P49V5933_17 Datasheet, PDF (1/33 Pages) Integrated Device Technology – Programmable Clock Generator | |||
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Programmable Clock Generator
5P49V5933
DATASHEET
Description
The 5P49V5933 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
5P49V5933 by default uses an integrated 25MHz crystal as
input reference. It also has a redundant external clock input.
A glitchless manual switchover functions allows selection of
either one as mentioned above as input reference during
normal operation
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
NC
NC
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2
17
3
16
EPAD
4
15
5
14
6
13
7 8 9 10 11 12
VDDA
NC
NC
VDDA
NC
NC
Features
⢠Generates up to two independent output frequencies
⢠High performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs:
â PCIe Gen1, 2, 3 compliant clock capability
â USB 3.0 compliant clock capability
â 1 GbE and 10 GbE
⢠Two fractional output dividers (FODs)
⢠Independent Spread Spectrum capability on each output
pair
⢠Two banks of internal non-volatile in-system programmable
or factory programmable OTP memory
⢠I2C serial programming interface
⢠One reference LVCMOS output clock
⢠Two universal output pairs:
â Each configurable as one differential output pair or two
LVCMOS outputs
⢠I/O Standards:
â Single-ended I/Os: 1.8V to 3.3V LVCMOS
â Differential I/Os - LVPECL, LVDS and HCSL
⢠Input frequency ranges:
â LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) â 1MHz to 350MHz
⢠Output frequency ranges:
â LVCMOS Clock Outputs â 1MHz to 200MHz
â LVDS, LVPECL, HCSL Differential Clock Outputs â
1MHz to 350MHz
⢠Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
⢠Redundant clock inputs with manual switchover
⢠Programmable loop bandwidth
⢠Programmable output to output skew
⢠Programmable slew rate control
⢠Individual output enable/disable
⢠Power-down mode
⢠1.8V, 2.5V or 3.3V core VDDD, VDDA
⢠Available in 24-pin VFQFPN 4mm x 4mm package
⢠-40° to +85°C industrial temperature operation
24-pin VFQFPN
5P49V5933 MARCH 10, 2017
1
©2017 Integrated Device Technology, Inc.
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