5P49V5907_16 Datasheet, PDF (1/30 Pages) Integrated Device Technology – Programmable Clock Generator

Programmable Clock Generator
5P49V5907
DATASHEET
Description
The 5P49V5907 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I²C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock^® 5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
The device may be configured to use one of two I²C
addresses to allow multiple devices to be used in a system.
Pin Assignment
NC
XOUT
XIN/REF
V_DDA
V_DDO
OUT7
OUT7B
OUT6
OUT6B
SD/OE
40 39 38 37 36 35 34 33 32 31
1
30
2
29
3
28
4
27
5
26
EPAD
6
25
7
24
8
23
9
22
10
21
11 12 13 14 15 16 17 18 19 20
V_DDO2
OUT2
OUT2B
V_DD
V_DD
V_{DD_CORE}
OUT3
OUT3B
NC
NC
40-pin VFQFPN
Features
• Generates up to four independent output frequencies with a
total of 7 differential outputs and one reference output
• Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency of
each output pair can be individually programmed
– Four copies of Low Power HCSL(LP-HCSL) outputs.
• Programmable frequency:
– See Output Features and Descriptions for details
• One reference LVCMOS output clock
• High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Four fractional output dividers (FODs)
• Independent Spread Spectrum capability from each
fractional output divider (FOD)
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
• I²C serial programming interface
• Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LP-HCSL Clock Outputs – 1MHz to 200MHz
– Other Differential Clock Outputs – 1MHz to 350MHz
• Programmable loop bandwidth
• Programmable crystal load capacitance
• Power-down mode
• Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 4 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
– See Pin Descriptions for details
• Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)
• -40° to +85°C industrial temperature operation
5P49V5907 NOVEMBER 11, 2016
1
©2015 Integrated Device Technology, Inc.