5P35023 Datasheet, PDF (1/34 Pages) Integrated Device Technology – VersaClock Programmable Clock Generator

VersaClock^® Programmable Clock Generator
5P35023
DATASHEET
General Description
The 5P35023 is a VersaClock programmable clock generator
and is designed for low power, consumer, and
high-performance PCI Express applications. The 5P35023
device is a three PLL architecture design, and each PLL is
individually programmable and allowing for up to six unique
frequency outputs.
The 5P35023 has built-in unique features such as Proactive
Power Saving (PPS), Performance-Power Balancing (PPB),
Overshot Reduction Technology (ORT) and Extreme Low
Power DCO. An internal OTP memory allows the user to store
the configuration in the device. After power up, the user can
change the device register settings through the I2C interface
when I2C mode is selected.
The device has programmable VCO and PLL source selection
to allow the user to do power-performance optimization based
on the application requirements. It also supports three
single-ended outputs and two pair of differential outputs that
support LVCMOS, LVPECL, LVDS and LPHCSL. A Low
Power 32.768kHz clock is supported with only less than 2µA
current consumption for system RTC reference clock.
Recommended Application
• PCIe Gen1/2/3 clock generator
• Consumer application crystal replacements
• SmartDevice, Handheld, Computing and Consumer
applications
Features/Benefits
• Configurable OE pin function as OE, PD#, PPS or DFC
control function
• Configurable PLL bandwidth/minimizes jitter peaking
• PPS: Proactive Power Saving features save power during
the end device power down mode
• PPB: Performance- Power Balancing feature allows
minimum power consumption base on required
performance
• DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 difference
frequencies smoothly
• Two PLLs support independent Spread Spectrum clocks to
lower system EMI
• Store user configuration into OTP memory
• I²C interface
Key Specifications
• PCIe clocks phase jitter: PCIe Gen3
• Differential clocks <3 ps rms jitter integer range
12KHz~20MHz
Output Features
• 2 – DIFF outputs with configurable LPHSCL, LVDS,
LVPECL, LVCMOS output pairs. 1MHz~500MHz (160MHz/
with LVCMOS mode)
• 3 – LVCMOS outputs; 1MHz~160MHz
• Maximum 8 LVCMOS outputs as REF + 3* SE +
2*DIFF_T/C as LVCMOS
• Low Power 32.768kHz clock supported for all SE1~SE3
Pin Assignment
24 23 22 21 20 19
VDDA 1
18 DIFF1
SDA_DFCO 2
17 DIFF1B
SEL_DFC/SCL_DFC1 3
CLKIN/X2 4
5P35023
16 VDDDIFF1
15 _OE1
CLKINB/X1 5
14 SE1
VBAT 6
13 VDDSE1
7
8
9 10 11 12
5P35023 MAY 26, 2016
24-pin VFQFPN
1
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