5L35023 Datasheet, PDF (1/38 Pages) Integrated Device Technology – Clock Generator

VersaClock^® 3S Programmable
Clock Generator
5L35023
Datasheet
Description
The 5L35023 is a member of the VersaClock^® 3S programmable
clock generator family with 1.8V operation voltage, and is
designed for industrial, consumer, and PCI Express applications.
The device features a 3 PLL architecture design; each PLL is
individually programmable and allowing up to 6 unique frequency
outputs.
The 5L35023 has built-in features such as Proactive Power
Saving (PPS), Performance-Power Balancing (PPB), Overshot
Reduction Technology (ORT) and extreme low power DCO. An
internal OTP memory allows the user to store the configuration in
the device without programming after power-up, then program the
5L35023 again through the I²C interface.
The device has programmable VCO and PLL source selection,
allowing power-performance optimization based on the application
requirements.
Typical Applications
▪ Embedded computing devices
▪ Consumer application crystal oscillator replacements
▪ SmartDevice, Handheld, and Consumer applications
Key Specifications
▪ PCIe Gen1/2/3 compliant
▪ Typical 1.5ps rms jitter integer range: 12kHz–20MHz
▪ Typical ultra-power-down current 50μA
▪ < 2μA RTC clock in Suspend Mode operation
Block Diagram
Features
▪ Configurable OE pin function as OE, PD#, PPS or DFC control
function
▪ Configurable PLL bandwidth; minimizes jitter peaking
▪ PPS: Proactive Power Saving features save power during the
end device power down mode
▪ PPB: Performance Power Balancing feature allows minimum
power consumption based on required performance
▪ DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 different frequencies
smoothly
▪ Spread spectrum clock to lower system EMI
▪ I²C interface
▪ Suspend Mode, featuring RTC clock only when system goes
into low-power operation modes
Output Features
▪ 2 DIFF outputs with configurable LPHSCL, LVCMOS output
pairs: 1MHz–125MHz
▪ 3 LVCMOS outputs: 1MHz–125MHz
▪ LVPECL, LVDS, CML and SSTL logic can be easily supported
with the LP-HCSL outputs. See application note AN-891 for
alternate terminations
▪ Maximum of 8 LVCMOS outputs
▪ Low-power 32.768kHz clock supported for all SE1–SE3
CLKIN/X1
X2
SEL_DFC/ SCL_DFC1
SDA_DFC0
OSC
Programmable
Load Capacitor
VDD18
VDDA
VBAT
Calibration
32.768K
DCO
PLL1
PLL2
PLL3
Mux
&
Divider
REF
VDDDIFF1
DIFF1
DIFF1B
VDDDIFF2
DIFF2
DIFF2B
VDDSE1
SE1
OE1
VDDSE2
SE2
OE2
VDDSE3
SE3
OE3
©2017 Integrated Device Technology, Inc.
1
July 13, 2017