5P49V5908_17 Datasheet, PDF (9/30 Pages) Integrated Device Technology – Programmable Clock Generator

5P49V5908 DATASHEET
Table 5: I²C Bus DC Characteristics
Symbol
V_IH
Parameter
Input HIGH Level
V_IL
V_HYS
I_IN
V_OL
Input LOW Level
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
Conditions
Min
Typ
Max
Unit
For SEL1/SDA pin
and SEL0/SCL pin.
For SEL1/SDA pin
and SEL0/SCL pin.
0.7xVDDD
GND-0.3
5.5 ²
V
0.3xVDDD
V
0.05xVDDD
V
-1
30
µA
I_OL = 3 mA
0.4
V
Table 6: I²C Bus AC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
F_SCLK Serial Clock Frequency (SCL)
10
400
kHz
t_BUF
Bus free time between STOP and START
1.3
µs
t_SU:START Setup Time, START
0.6
µs
t_HD:START Hold Time, START
0.6
µs
t_SU:DATA
t_HD:DATA
Setup Time, data input (SDA)
Hold Time, data input (SDA) ¹
100
ns
0
µs
t_OVD
Output data valid from clock
0.9
µs
C_B
Capacitive Load for Each Bus Line
400
pF
t_R
Rise Time, data and clock (SDA, SCL)
20 + 0.1xC_B
300
ns
t_F
Fall Time, data and clock (SDA, SCL)
20 + 0.1xC_B
300
ns
t_HIGH
HIGH Time, clock (SCL)
0.6
µs
t_LOW
LOW Time, clock (SCL)
1.3
µs
t_SU:STOP Setup Time, STOP
0.6
µs
Note 1: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IH(MIN) of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
Note 2; I2C inputs are 5V tolerant.
MARCH 10, 2017
9
PROGRAMMABLE CLOCK GENERATOR