5P35023_17 Datasheet, PDF (26/34 Pages) Integrated Device Technology – Programmable Clock Generator

5P35023 DATASHEET
Byte15: Output divider1 control
Byte 0Fh
Name
Control Function
Type
0
Bit 7
OUTDIV1[3]
Output divider1 control bit 3
R/W
-
Bit 6
OUTDIV1[2]
Output divider1 control bit 2
R/W
-
Bit 5
OUTDIV1[1]
Output divider1 control bit 1
R/W
-
Bit 4
OUTDIV1[0]
Output divider1 control bit 0
R/W
-
Bit 3
OUTDIV2[3]
Output divider2 control bit 3
R/W
-
Bit 2
OUTDIV2[2]
Output divider2 control bit 2
R/W
-
Bit 1
OUTDIV2[1]
Output divider2 control bit 1
R/W
-
Bit 0
OUTDIV2[0]
Output divider2 control bit 0
R/W
-
Byte16: PLL2 integer feedback divider
Byte 10h
Name
Control Function
Type
0
Bit 7
reserved
-
R/W
-
Bit 6
reserved
-
R/W
-
Bit 5
reserved
-
R/W
-
Bit 4
reserved
-
R/W
-
Bit 3
reserved
-
R/W
-
Bit 2
PLL2_FB_INT[10]
PLL2 feedback integer divier 10
R/W
-
Bit 1
PLL2_FB_INT[9]
PLL2 feedback integer divier 9
R/W
-
Bit 0
PLL2_FB_INT[8]
PLL2 feedback integer divier 8
R/W
-
Byte17: PLL2 integer feedback divider
Byte 11h
Name
Control Function
Type
0
Bit 7
PLL2_FB_INT_DIV[7]
PLL2 feedback integer divier 7
R/W
-
Bit 6
PLL2_FB_INT_DIV[6]
PLL2 feedback integer divier 6
R/W
-
Bit 5
PLL2_FB_INT_DIV[5]
PLL2 feedback integer divier 5
R/W
-
Bit 4
PLL2_FB_INT_DIV[4]
PLL2 feedback integer divier 4
R/W
-
Bit 3
PLL2_FB_INT_DIV[3]
PLL2 feedback integer divier 3
R/W
-
Bit 2
PLL2_FB_INT_DIV[2]
PLL2 feedback integer divier 2
R/W
-
Bit 1
PLL2_FB_INT_DIV[1]
PLL2 feedback integer divier 1
R/W
-
Bit 0
PLL2_FB_INT_DIV[0]
PLL2 feedback integer divier 0
R/W
-
Byte18: PLL2 fractional feedback divider
Byte 12h
Name
Control Function
Type
0
Bit 7
PLL2_FB_FRC_DIV[7]
PLL2 feedback fractional divier 7
R/W
-
Bit 6
PLL2_FB_FRC_DIV[6]
PLL2 feedback fractional divier 6
R/W
-
Bit 5
PLL2_FB_FRC_DIV[5]
PLL2 feedback fractional divier 5
R/W
-
Bit 4
PLL2_FB_FRC_DIV[4]
PLL2 feedback fractional divier 4
R/W
-
Bit 3
PLL2_FB_FRC_DIV[3]
PLL2 feedback fractional divier 3
R/W
-
Bit 2
PLL2_FB_FRC_DIV[2]
PLL2 feedback fractional divier 2
R/W
-
Bit 1
PLL2_FB_FRC_DIV[1]
PLL2 feedback fractional divier 1
R/W
-
Bit 0
PLL2_FB_FRC_DIV[0]
PLL2 feedback fractional divier 0
R/W
-
Byte19: PLL2 fractional feedback divider
Byte 13h
Name
Control Function
Type
0
Bit 7
PLL2_FB_FRC_DIV[15]
PLL2 feedback fractional divier 15
R/W
-
Bit 6
PLL2_FB_FRC_DIV[14]
PLL2 feedback fractional divier 14
R/W
-
Bit 5
PLL2_FB_FRC_DIV[13]
PLL2 feedback fractional divier 13
R/W
-
Bit 4
PLL2_FB_FRC_DIV[12]
PLL2 feedback fractional divier 12
R/W
-
Bit 3
PLL2_FB_FRC_DIV[11]
PLL2 feedback fractional divier 11
R/W
-
Bit 2
PLL2_FB_FRC_DIV[10]
PLL2 feedback fractional divier 10
R/W
-
Bit 1
PLL2_FB_FRC_DIV[9]
PLL2 feedback fractional divier 9
R/W
-
Bit 0
PLL2_FB_FRC_DIV[8]
PLL2 feedback fractional divier 8
R/W
-
VERSACLOCK^® PROGRAMMABLE CLOCK GENERATOR
26
1
PWD
-
0
-
0
-
1
-
1
-
0
-
0
-
1
-
1
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
1
PWD
-
0
-
0
-
1
-
0
-
1
-
0
-
0
-
0
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
JANUARY 25, 2017