5P49V5913_17 Datasheet, PDF (11/37 Pages) Integrated Device Technology – Programmable Clock Generator

5P49V5913 DATASHEET
Table 6: I²C Bus DC Characteristics
Symbol
Parameter
V_IH
Input HIGH Level
V_IL
Input LOW Level
V_HYS
I_IN
V_OL
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
Conditions
For SEL1/SDA pin and
SEL0/SCL pin.
For SEL1/SDA pin and
SEL0/SCL pin.
I_OL = 3 mA
Min
0.7xV_DDD
GND-0.3
0.05xV_DDD
-1
Typ
Max
5.5 ²
Unit
V
0.3xV_DDD V
V
30
µA
0.4
V
Table 7: I²C Bus AC Characteristics
Symbol
F_SCLK
t_BUF
t_SU:START
t_HD:START
t_SU:DATA
t_HD:DATA
t_OVD
C_B
t_R
t_F
t_HIGH
t_LOW
t_SU:STOP
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Hold Time, START
Setup Time, data input (SDA)
Hold Time, data input (SDA) ¹
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCL)
Fall Time, data and clock (SDA, SCL)
HIGH Time, clock (SCL)
LOW Time, clock (SCL)
Setup Time, STOP
Min
Typ
10
1.3
0.6
0.6
0.1
0
20 + 0.1xC_B
20 + 0.1xC_B
0.6
1.3
0.6
Max
400
0.9
400
300
300
Unit
kHz
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
µs
µs
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH(MIN) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
Note 2: I²C inputs are 5V tolerant.
MARCH 3, 2017
11
PROGRAMMABLE CLOCK GENERATOR