5P35021_17 Datasheet, PDF (1/34 Pages) Integrated Device Technology – Programmable Clock Generator

VersaClock^® Programmable Clock Generator
5P35021
DATASHEET
General Description
The 5P35021 is the latest VersaClock programmable clock
generator and is designed for low-power, consumer, and
high-performance PCI Express applications. The 5P35021
device is a 3 PLLs architecture design; each PLL is
individually programmable and allows up to 3 unique
frequency outputs.
The 5P35021 has built-in unique features such as Proactive
Power Saving (PPS), Performance-Power Balancing (PPB),
Overshot Reduction Technology (ORT) and Extreme Low
Power DCO. An internal OTP memory allows the user to store
the configuration in the device. After power up, the user can
change the device register settings through the I²C interface
when I2C mode is selected. It also has programmable VCO
and PLL source selection to allow the user to do
power-performance optimization based on the application
requirements.
The device provides one single-ended output and two pairs of
differential outputs that support LVCMOS, LVPECL, LVDS and
LPHCSL. The Low Power 32.768KHZ clock is supported with
only less than 2uA current consumption for system RTC
reference clock.
Recommended Application
• PCIe Gen1/2/3 clock generator
• Consumer application crystal replacements
• SmartDevice, Handheld, Computing and Consumer
applications
Features/Benefits
• Configurable OE pin function as OE, PD#, PPS or DFC
control function
• Configurable PLL bandwidth/minimizes jitter peaking
• PPS: Proactive Power Saving features save power during
the end device power down mode
• PPB: Performance- Power Balancing feature allow user to
minimum power consumption base on required
performance
• DFC: Dynamic Frequency Control feature allows user to
program up to 4 difference frequencies and switch
dynamically
• Spread Spectrum clock support to lower system EMI
• Store user configuration into OTP memory
• I²C interface
Key Specifications
• PCIe clocks phase jitter: PCIe Gen3
• Differential clocks <3 ps rms jitter integer range
12KHz~20MHz
• <2µA DCO to generate 32.768kHz clock
Output Features
• 2 – DIFF outputs with configurable LPHSCL, LVDS,
LVPECL, LVCMOS output pairs. 1MHz~500MHz (160MHz/
with LVCMOS mode)
• 1 – LVCMOS output, 1MHz~160MHz
• Maximum 5 LVCMOS outputs as 1* SE + 2*DIFF_T/C as
LVCMOS
• Low Power 32.768kHz clock supported on SE1
Pin Assignment
20
VDDA 1
SDA_DFCO ²
SEL_DFC/SCL_DFC1 ³
CLKIN/X2 ⁴
CLKINB/X1 ⁵
6
19
18
17
16
15 DIFF1
14 DIFF1B
5P35021
13 VDDDIFF1
12 OE1
11 SE1
7
8
9
10
5P35021 JANUARY 25, 2017
1
©2017 Integrated Device Technology, Inc.