ICS854058 Datasheet, PDF (9/12 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS854058
8:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
SCHEMATIC EXAMPLE
An application schematic example of ICS854058 is shown
in Figure 4. The inputs can accept various types of differential
signals. In this example, the inputs are driven by LVDS drivers.
The transmission lines are assumed to be 100Ω differential.
The 100Ω matched loads termination should be located
near the receivers. It is recommended at least one
decoupling capacitor per power pin. The decoupling ca-
pacitor should be low ESR and located as close as pos-
sible to the power pin.
Zo = 50
LVDS
Zo = 50
100 Ohm Differential
100 Ohm Differential
Zo = 50
R2
100
Zo = 50
LVDS
C1
0.1u
3.3V
U1
1
2 ^PCLK0
3
4
5
nPCLK0
PCLK1
nPCLK1
6 ^VDD
7
8
9
SEL0
SEL1
SEL2
10 ^PCLK2
11 ^nPCLK2
12
PCLK3
nPCLK3
ICS854058
Logic Control Input Examples
Set Logic
Set Logic
R1
VDD _{Input to}
VDD _{Input to}
100
'1'
'0'
RU1
1K
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
24
PCLK7
nPCLK7
PCLK6
nPCLK6
23
22
21
20
VDD ₁₉
Q0
nQ0
GND
18
17
16
PCLK5
nPCLK5
15
14
PCLK4
nPCLK4
13
3.3V
C2
0.1u
Zo = 50
R3
100
Zo = 50
100 Ohm Dif f erential
+
-
LVDS
FIGURE 4. ICS854058 SCHEMATIC EXAMPLE
854058AG
www.icst.com/products/hiperclocks.html
9
REV. A APRIL 8, 2004