ICS8521I-03 Datasheet, PDF (9/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8521I-03
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER, GROUND AND BYPASS CAPACITOR
This section provides a layout guide related to power, ground
and placement of bypass capacitors for a high-speed digital IC.
This layout guide is a general recommendation. The actual board
design will depend on the component types being used, the board
density and cost constraints. This description assumes that the
board has clean power and ground planes. The goal is to mini-
mize the ESR between the clean power/ground plane and the
IC power/ground pin. A low ESR bypass capacitor should be
used on each power pin. The value of bypass capacitors ranges
from 0.01uF to 0.1uF. The bypass capacitors should be located
as close to the power pin as possible. It is preferable to locate
the bypass capacitor on the same side as the IC. Figure 3B
shows suggested capacitor placement. Placing the bypass ca-
pacitor on the same side as the IC allows the capacitor to
have direct contact with the IC power pin. This can avoid any
vias between the bypass capacitor and the IC power pins. The
vias should be placed at the Power/Ground pads. There should
be a minimum of one via per pin. Increasing the number of vias
from the Power/Ground pads to Power/Ground planes can im-
prove the conductivity
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL Driv er
R9
50
VD D=3. 3V
C5
0.1u
R12 1K
R 10
50
R11 1K
VDD=3.3V
VD DO=1. 8V
C1
0.1u
U1
1
2 ^VDD
3
4
5
CLK0
nCLK0
CLK_SEL
6
7
8
CL:K1
nCLK1
GND
CLK_EN
IC S8521I -03
C3
0.1u
Zo = 50
VDDO=1.8V
C2
0.1u
Zo = 50
C6
0.1u
+
-
R2
R1
50
50
24
VDDO ₂₃
Q3
nQ3
Q4
22
21
20
nQ4
Q5
nQ5
VD DO
19
18
17
VDDO=1.8V
C4
0.1u
C7
0.1u
Zo = 50
Zo = 50
+
-
R8
R7
50
50
FIGURE 3B. RECOMMENDED LAYOUT OF BYPASS CAPACITOR PLACEMENT
8521AYI-03
www.icst.com/products/hiperclocks.html
9
REV. A APRIL 29, 2003