ICS1574B Datasheet, PDF (9/12 Pages) Integrated Circuit Systems – User Programmable Laser Engine Pixel Clock Generator

BIT(S)
45
46
BIT REF.
Reserved
PCLK_EN
47, 48
49 – 55
56
Reserved
R[0]..R[6]
REF_POL
ICS1574B
DESCRIPTION
Must be set to 1.
Must be set to 0.
Disables the PCLK divider when set to 1 regardless of
PCLKEN input state.
Must be set to 0.
Reference divider modulus control bits.
Modulus = value +1.
PLL locks to rising edge of XTAL1 input when
REFPOL = 1, falling edge of XTAL1 when REFPOL = 0.
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