ICS93732 Datasheet, PDF (8/8 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9373 2
N
INDEX
AREA
12
D
A2
e
b
c
E1 E
A
A1
-C-
SEATING
PLANE
aaa C
L
α
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
In Millimeters
COMMON DIMENSIONS
MIN
MAX
--
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
--
0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
--
.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
--
.004
VARIATIONS
N
D mm.
MIN
MAX
28
9.60
9.80
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
D (inch)
MIN
MAX
.378
.386
4.40 mm. Body, 0.65 mm. pitch TSSOP
(173 mil)
(0.0256 Inch)
Ordering Information
ICS93732yG -T
Example:
ICS XXXX y G - T
0578H—02/19/04
Designation for tape and reel packaging
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
8