ICS8535-31 Datasheet, PDF (8/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8535-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
CRYSTAL INPUT INTERFACE
The ICS8535-31 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 3 below were determined using an 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
These same capacitor values will tune any 18pF parallel reso-
nant crystal over the frequency range and other parameters
specified in this data sheet. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
8535AG-31
X1
18pF Parallel Crystal
XTAL_IN
C1
18p
XTAL_OUT
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
www.icst.com/products/hiperclocks.html
8
REV. B APRIL 29, 2005