74HCT40103 Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – 8-bit synchronous binary down counter

Philips Semiconductors
8-bit synchronous binary down counter
Product specification
74HC/HCT40103
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I_CC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.
To determine ∆I_CC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP, PE
1.50
MR
1.00
TE
0.80
PL
0.35
P_n
0.25
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
T_amb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t_PHL/ t_PLH propagation delay
CP to TC
35 60
75
90 ns 4.5 Fig.7
t_PHL/ t_PLH propagation delay
TE to TC
23 40
50
60 ns 4.5 Fig.8
t_PHL/ t_PLH propagation delay
PL to TC
44 75
94
112 ns 4.5 Fig.9
t_PHL
propagation delay
MR to TC
29 55
69
83 ns 4.5 Fig.9
t_THL/ t_TLH output transition time
7 15
19
22 ns 4.5 Figs. 7 and 8
t_W
clock pulse width
33 10
41
50
ns 4.5 Fig.7
HIGH or LOW
t_W
master reset pulse width 30 16
38
45
ns 4.5 Fig.9
LOW
t_W
preset enable pulse width 38 22
48
57
ns 4.5 Fig.9
PL; LOW
t_rem
removal time
10 1
13
15
ns 4.5 Fig.10
MR to CP or PL to CP
t_su
set-up time
PE to CP
20 11
25
30
ns 4.5 Fig.11
t_su
set-up time
TE to CP
40 20
50
60
ns 4.5 Fig.11
1998 Jul 08
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