ICS950401 Datasheet, PDF (7/14 Pages) Integrated Circuit Systems – AMD - K8TM System Clock Chip

ICS950401
Byte 7: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
0 Reserved
Bit5 -
0 Reserved
Bit4 -
1 Reserved
Bit3 -
0 Reserved
Bit2 -
0 Reserved
Bit1 -
0 Reserved
Bit0 -
0 Reserved
Byte 8: Single Pulse Mode Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Single Pulse Trigger
Bit6 -
0 Single Pulse Activate
Bit5 -
0 (Reserved)
Bit4 -
0 (Reserved)
Bit3 -
0 (Reserved)
Bit2 -
0 (Reserved)
Bit1 -
0 (Reserved)
Bit0 -
0 (Reserved)
Notes:
ATPG Function: This feature is only used during processor Burn-In and is an optional feature
for the clk vendor to implement.
Two SMBus register bits are required to implement this feature:
ATPG Mode Bit: Enables/Disables ATPG mode
ATPG Pulse Bit: Triggers a single CPUclk pulse when set
Assuming that the clock synthesizer is operating either in Normal mode or PLL bypass
mode, following sequence may be followed to generate an ATPG pulse.
1. Set the Write Enable Bit (Byte/Bit 0) to program the Clock Synthesizer registers using
the SM Bus.
2. Use the ATPG Mode Bit in the clock synthesizer configuration space to enable/disable
the ATPG mode. When this bit is set, the ATPG mode is enabled and the differential
CPU clock outputs are pulled in differential low state (CPUT = 0 and CPUC = 1). The
ATPG mode also requires the USBclk (48MHz) to run as usual. All other clks (PCI,
Ref, PCI33_66, SuperIO are not used by the ATPG mode therefore can either be left
running or shut off.
3. Use the ATPG Pulse Bit in the clock synthesizer program space to generate the ATPG
pulse. When the ATPG Pulse Bit is set, a differential ATPG pulse will be generated on
the differential CPU clock pins. The pulse width of the ATPG pulse will be one CPU
clock period. The CPU clock period in the ATPG mode is same as the one in Normal
mode or PLL bypass mode.
4. Clear the ATPG Pulse Bit, as the clock synthesizer only recognizes 0 to 1 transition of
the ATPG pulse bit for next ATPG pulse generation.
5. Use the ATPG Pulse Bit to generate the next ATPG pulse (set to 1).
6. If the ATPG Pulse bit is not set and the ATPG Mode Bit is cleared then the synthesizer
should work in normal or PLL bypass mode.
0499C—11/01/04
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