ICS94228 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – Programmable System Clock Chip for AMD - K7™ processor

ICS94228
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
42, 41
39, 38
6
7
-
28
27
26
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
CPUCLKT0, CPUCLKC0
CPUCLK_CST0, CPUCLK_CSC0
48MHz
24_48MHz
FS0 (readback)
AGP2
AGP1
AGP0
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
20
18
17
16
14
13
11
10
PWD
DESCRIPTION
1 PCICLK7
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 3: PCI, REF, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Watch Dog Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
9
22
-
21
46
-
47
48
PWD
DESCRIPTION
1 PCICLK_F
1 PCICLK9_E
1 FS1 (readback)
1 PCICLK8
1 REF_F
1 FS2 (readback)
1 REF1
1 REF0
Byte 5: Vendor Specific Feature, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
0 SEL24_48# (readback)
-
0 FS3 (readback)
-
0
Watchdog status:
0=Normal 1=Alarm
-
1 SSB1
-
1 FS3
-
1 FS2
-
1 FS1
-
1 FS0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
BIT PIN# PWD
DESCRIPTION
Bit 7 -
Watch dog enable
0 0: stop
1: start
Bit 6 -
0 M/N program enable
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2 -
Bit 1 -
Bit 0 -
0 The decimal representation of
0 ^{these 8 bits correspond to}
290ms or 1ms the watchdog
1 _{timer will wait before it goes}
0 ^{to alarm mode and reset the}
0
frequency to the safe setting.
Default at power up is 8X
0 580ms = 4.6 seconds.
Byte 6: Vendor ID1 , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0
Bit6 -
Bit5 -
0
Device ID
0
Bit4 -
1
Bit3 -
0
Bit2 -
Bit1 -
0
Vendor ID
0
Bit0 -
1
Note: Don’t write into this register, writing into this
register can cause malfunction
0447E—05/07/04
7