ICS9248-66 Datasheet, PDF (7/11 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II Systems

ICS9248-66
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Offset
Group
Offset
CPU to 3V66
0.0-1.5ns CPU leads
3V66 to PCI
1.5-4.0ns 3V66 leads
CPU to IOAPIC 1.5-4.0ns CPU leads
No te: 1 . All o ffsets are to be meas u red at ris in g edg es.
Measurement Loads
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
CPU @ 20pF, IOAPIC @ 20pF
Measure Points
CPU @1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU @1.25V, IOAPIC @ 1.5V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Input High Voltage
V_IH
2
V_DD+0.
3
Input Low Voltage
V_IL
V_SS-0.3
0.8
Input High Current
I_IH
V_IN = V_DD
-5
5
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-up resistors
Input Low Current
Operating Supply
Current
I_IL2
I_DD3.3OP
V_IN = 0 V; Inputs with pull-up resistors
C_L = 0 pF; Select
Power Down Supply
Current
I_DD3.3PD C_L = 0 pF; With input address to Vdd or GND
Input frequency
F_i
V_DD = 3.3 V;
14.318
Pin Inductance
L_pin
7
C_IN Logic Inputs
5
Input Capacitance¹
C_out Out put pin capacitance
6
C_INX X1 & X2 pins
27
45
Transition Time¹
T_trans To 1st crossing of target Freq.
3
Settling Time¹
T_s
From 1st crossing to 1% target Freq.
Clk Stabilization¹
T_STAB From V_DD = 3.3 V to 1% target Freq.
3
Delay
t_PZH,t_PZH output enable delay (all outputs)
t_PLZ,t_PZH output disable delay (all outputs)
1_{Guarenteed by design, not 100% tested in production.}
1
10
1
10
UNITS
V
V
µA
µA
µA
mA
µA
MHz
nH
pF
pF
pF
mS
mS
mS
nS
nS
7