ICS853210 Datasheet, PDF (7/15 Pages) Integrated Circuit Systems – LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1A shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level V_BB generated from the device is connected to the
negative input. The C1 capacitor should be located as close
as possible to the input pin.
CLK_IN
VCC(or VDD)
PCLK
VBB
nPCLK
FIGURE 1A. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1B shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V_CC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
PCLK
nPCLK
R2
1K
853210AY
FIGURE 1B. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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7
REV. A NOVEMBER 12, 2003