ICS843251I-12 Datasheet, PDF (7/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843251I-12
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843251I-12 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V and V
CC
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V_CCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V or 2.5V
V_CC
.01μF 10Ω
V_CC
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843251I-12 has been characterized with 18pF par-
allel resonant crystals. The capacitor values (TBD), C1 and
C2, shown in Figure 2 below were determined using a
25MHz, 18pF parallel resonant crystal and were chosen to
minimize the ppm error. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
X1
Crystal
XTAL_IN
C1
XTAL_OUT
C2
Figure 2. CRYSTAL INPUt INTERFACE
843251BGI-12
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 10, 2006