ICS843021 Datasheet, PDF (7/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS843021
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843021. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 27pF and C2 = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
VCC
R2
10 C3
10uF
C2
33pF
25MHz
18pF
VCCA
C4
0.01u
X1
U1
1
2
3
4
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
NC
8
7
6
5
ICISC8S48340320111
C1
27pF
VCC=3.3V
VCC
VCC
R3
133
Zo = 50 Ohm
Q
Zo = 50 Ohm
nQ
C5
0.1u
R4
82.5
R5
133
+
-
R6
82.5
FIGURE 3A. ICS843021 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843021 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843021 PC BOARD LAYOUT EXAMPLE
843021AG
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REV. C MARCH 31, 2005