ICS97ULP844A Datasheet, PDF (6/12 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS97UL P 8 44A
Timing Requirements
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Max clock frequency
freq_op
1.8V+0.1V @ 25°C
95
Application Frequency
Range
freq_App
1.8V+0.1V @ 25°C
160
Input clock duty cycle
d_{t in}
40
CLK stabilization
T_STAB
2.4
MAX
370
350
60
2.95
Switching Characteristics¹
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
Output enable time
t_en
OE to any output
Output disable time
t_dis
OE to any output
Period jitter
t_{jit (per)}
-30
Half-period jitter
Input slew rate
t_jit(hper)
-60
Input Clock
1
SLr1(i)
Output Enable (OE), (OS)
0.5
Output clock slew rate
SLr1(o)
1.5
Cycle-to-cycle period jitter
t_jit(cc+)
0
t_jit(cc-)
0
Dynamic Phase Offset
t_{( )dyn}
-20
Static Phase Offset
t_SPO2
-50
Output to Output Skew
t_skew
SSC modulation frequency
30.00
SSC clock input frequency
0.00
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
TYP MAX UNITS
4.73
8
ns
5.82
8
ns
30
ps
60
ps
2.5
4
v/ns
v/ns
2.5
3
v/ns
40
ps
-40
ps
20
ps
0
50
ps
50
ps
33 kHz
-0.50 %
MHz
1110B—06/06/05
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