ICS95V857C Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)

ICS95V8 5 7 C
Timing Requirements
T_A = 0 - 85°C; Supply Voltage A_VDD, V_DD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freq_op
2.5V+0.2V @ 25^oC
45
233
Application Frequency
Range
freq_App
2.5V+0.2V @ 25^oC
95
220
Input clock duty cycle
d_tin
40
60
UNITS
MHz
MHz
%
CLK stabilization
T_STAB
15
µs
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN TYP
Low-to high level
propagation delay time
t_PLH1
CLK_IN to any output
3.5
High-to low level propagation
delay time
t_PLL1
CLK_IN to any output
3.5
Output enable time
t_EN
PD# to any output
3
Output disable time
tdis
PD# to any output
3
Period jitter
Half-period jitter
T_{jit (per)}
100MHz to 200MHz
-30
t(jit_hper) 100MHz to 200MHz
-75
Input clock slew rate
t_sl(i)
1
Output clock slew rate
t_sl(o)
1
Cycle to Cycle Jitter¹
T_cyc-T_cyc 100MHz to 200MHz
-50
Static Phase Offset
t_(static
phase
4
offset)
-50
0
Output to Output Skew
T_skew
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=t_wH/t_c, where
the cycle (t_c) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
MAX UNITS
ns
ns
ns
ns
30
ps
75
ps
4 V/ns
2 V/ns
50
ps
50
ps
40
ps
1190A—12/16/05
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