ICS9250-13 Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9250 - 13
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit Pin # PWD
Description
Bit 7
-
1 (Reserved)
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3 48
Bit 2 49
Bit 1 51
1 (Reserved)
X FS2#
X FS0#
1 CPUCLK3 (Act/Inact)
1 CPUCLK2 (Act/Inact)
1 CPUCLK1 (Act/Inact)
Bit 0 52
1 CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: Control Register
(1 = enable, 0 = disable)
Bit Pin # PWD
Description
Bit 7 36
1 SDRAM7 (Act/Inact)
Bit 6 37
1 SDRAM6 (Act/Inact)
Bit 5 39
1 SDRAM5 (Act/Inact)
Bit 4 40
1 SDRAM4 (Act/Inact)
Bit 3 42
1 SDRAM3 (Act/Inact)
Bit 2 43
1 SDRAM2 (Act/Inact)
Bit 1 45
1 SDRAM1 (Act/Inact)
Bit 0 46
1 SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Control Register
(1 = enable, 0 = disable)
Bit Pin # PWD
Description
Bit 7
-
1 (Reserved)
Bit 6
-
1 (Reserved)
Bit 5
-
1 (Reserved)
Bit 4
55
1 IOAPIC (Act/Inact)
Bit 3
-
X FS1#
Bit 2
-
1 (Reserved)
Bit 1
54
1 REF1 (Act/Inact)
Bit 0
2
1 REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit Pin # PWD
Description
Bit 7 -
X FS3#
Bit 6 7
1 PCICLK_F (Act/Inact)
Bit 5 15 1 PCICLK5 (Act/Inact)
Bit 4 13 1 PCICLK4 (Act/Inact)
Bit 3 12
1 PCICLK3 (Act/Inact)
Bit 2 11 1 PCICLK2 (Act/Inact)
Bit 1 10
1 PCICLK1 (Act/Inact)
Bit 0 8
1 PCICLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit Pin # PWD
Description
Bit 7
26
1 SDRAM15 (Act/Inact)
Bit 6
27
1 SDRAM14 (Act/Inact)
Bit 5
30
1 SDRAM13 (Act/Inact)
Bit 4
31
1 SDRAM12 (Act/Inact)
Bit 3
17
1 SDRAM11 (Act/Inact)
Bit 2
18
1 SDRAM10 (Act/Inact)
Bit 1
20
1 SDRAM9 (Act/Inact)
Bit 0
21
1 SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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