ICS9248-98 Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-98
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
40
-
43
44
PWD
DESCRIPTION
X Latched FS2#
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 SDRAM_F
1 (Reserved)
1 CPUCLK1
1 CPUCLK_F
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
7
-
13
12
11
10
8
PWD
DESCRIPTION
1 (Reserved)
1 PCICLK_F
1 (Reserved)
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
26
25
-
17, 18,
20, 21
28, 29,
31, 32
34, 35,
37, 38
PWD
DESCRIPTION
1 (Reserved)
X Latched FS0#
1 48MHz
1 24 MHz
1 (Reserved)
1 SDRAM (11:8)
1 SDRAM (7:4)
1 SDRAM (3:0)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
X Latched FS1#
1 (Reserved)
X Latched FS3#
1 (Reserved)
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
47
1 IOAPIC0
-
1 (Reserved)
-
1 (Reserved)
46
1 REF1
2
1 REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
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