ICS9248-81 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers

ICS9248 -81
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Description
Bit 7
0 - ±0.25% Center Spread Spectrum
1 - ±0.5% Center Spread Spectrum
Bit (2, 6:4) CPUCLK
SDRAM
PCICLK
PWD
1
Bit
(2, 6:4)
Bit 3
Bit 1
Bit 0
0000
90.00
90.00
30.00
0001
66.70
100.05
33.35
0010
95.00
63.33
31.66
0011
100.00
66.66
33.33
0100
100.00
75.00
30.00
0101
112.00
74.66
37.33
0110
124.00
82.66
31.00
0111
133.30
88.86
33.32
1000
66.70
66.70
33.35
1001
75.00
75.00
30.00
1010
83.30
83.30
33.32
1011
95.00
95.00
31.66
1100
100.00
100.00
33.33
1101
112.00
112.00
37.33
1110
124.00
124.00
31.00
1111
133.30
133.30
33.33
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread spectrum enabled
0 - Running
1 - Tristate all outputs
XXXX
Note 1
0
1
0
Note 1: Default at power-up will be for latched logic inputs to define frequency.
Note 2: PWD = Power-Up Default
6