ICS9158-05 Datasheet, PDF (6/7 Pages) Integrated Circuit Systems – Buffered Clock Generator for Pentium™ /Triton™ Systems

ICS9158-05
Advanced Information
ICS9158-05 CPU Clock DecodingTable
(using 14.318 MHz input. All frequencies in MHz)
VDD=5V±10% or 3.3V±10%, TEMP=0-70°C
OE PD# FS1 FS0
CPU
Ratio
X1,X2, CPU
REF (0:2)
(MHz) (MHz)
1 1 0 0 14/4xX1 14.318 50
1 1 0 1 14/3xX1 14.318 66.7
1 1 1 0 42/10xX1 14.318 60
1 1 1 1 (STOP) 14.318 Low
1
0
X
X
(PWR
DOWN)
Low
*Low
0 XXX
-
Tristate Tristate
BUS
(0:4)
(MHz)
25
33.3
30
Low
*Low
Tristate
PD# forces all outputs low and powers-down the oscillator
and PLL circuitry, minimizing power consumption. In order
to ensure glitch-free start and stop of the CPU and BUS
clocks, PD# should be asserted after the CPU and BUS clocks
have stopped, and be deasserted 10ms (maximum PLL lock
time) prior to starting the clocks.
Frequency Transitions
A key feature of the ICS9158-05 is its ability to provide
smooth, glitch-free frequency transitions on the CPU and
BUS clocks when the frequency select pins are changed. The
frequency transition rate does not violate the Intel 486 or
Pentium specification of less than 0.1% frequency change
per clock period.
Using an Input Clock as a Reference
The ICS9158-05 is designed to accept a 14.318 MHz crystal
as the input reference. With some external changes, it is
possi-ble to use a crystal oscillator or other clock sources.
Please see application note AAN04 for details on driving the
ICS9158-05 with a clock.
OE PD# FLOPPY (MHz) KEYBD (MHz)
1
1
24
12
1
0
Low
Low
0
X
Tristate
Tristate
6