ICS844256 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844256
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
F_OUT
tjit(Ø)
tsk(o)
Output Frequency
RMS Phase Jitter (Random)
Output Skew; NOTE 1, 2
125MHz, Integration Range:
1.875MHz - 20MHz
53.125
0.48
TBD
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
50
t_LOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
333.33
1
Units
MHz
ps
ps
ps
%
ms
TABLE 6B. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, V_DDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
F_OUT
tjit(Ø)
tsk(o)
Output Frequency
RMS Phase Jitter (Random)
Output Skew; NOTE 1, 2
125MHz, Integration Range:
1.875MHz - 20MHz
53.125
0.44
TBD
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
50
t
LOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
333.33
1
Units
MHz
ps
ps
ps
%
ms
844256AM
www.icst.com/products/hiperclocks.html
6
REV. A NOVEMBER 29, 2005