ICS348 Datasheet, PDF (6/7 Pages) Integrated Circuit Systems – Quad PLL Field Programmable VersaClock Synthesizer

ICS348
Quad PLL Field Programmable VersaClock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
F_IN Fundamental Crystal
5
Input Clock
2
Output Frequency
VDD=3.3 V
0.25
Output Rise Time
Output Fall Time
Duty Cycle
t_OR 20% to 80%, Note 1
t_OF 80% to 20%, Note 1
Note 2
1
1
40 49-51
Output Frequency Synthesis
Error
Configuration Dependent
TBD
Power-up time
PLL lock-time from
3
power-up, Note 3
PDTS goes high until
0.2
stable CLK output, Note 3
One Sigma Clock Period Jitter
Configuration Dependent
50
Maximum Absolute Jitter
t_ja
Deviation from Mean.
Configuration Dependent
+200
Pin-to-Pin Skew
Low Skew Outputs
-250
Max.
27
50
200
60
10
2
250
Units
MHz
MHz
MHz
ns
ns
%
ppm
ms
ms
ps
ps
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS
transition high on select address change.
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θ_JA Still air
θ_JA 1 m/s air flow
θ_JA 3 m/s air flow
Thermal Resistance Junction to Case θ_JC
Min.
Typ.
135
93
78
60
Max.
Units
°C/W
°C/W
°C/W
°C/W
MDS 348 H
6
Revision 051705
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