ICS275 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – Triple PLL Field Programmable VCXO Clock Synthesizer

PRELIMINARY INFORMATION
ICS275
Triple PLL Field Programmable VCXO Clock Synthesizer
Parameter
Symbol
Conditions
Internal Pull-up Resistor
Internal Pull-down Resistor
Input Capacitance
R_PUS
R_PD
C_IN
S2:S0, PDTS
CLK outputs
Inputs
Min.
Typ.
190
120
4
Max.
Units
kΩ
kΩ
pF
Note 1: Example with 25 MHz crystal input with four outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
Output Frequency
F_IN Fundamental crystal
5
0.314
Crystal Pullability
F_P 0V< VIN < 3.3 V, Note 1, 100
Config. Dependent
VCXO Gain
VIN = VDD/2 + 1 V,
110
Note 1, Config.
Dependent
Output Rise/Fall Time
t_OF 80% to 20%, high drive,
1.0
Note 2
Output Rise/Fall Time
t_OF 80% to 20%, low drive,
2.0
Note 2
Duty Cycle
Note 3
40 49-51
Power-up time
PLL lock-time from
4
power-up
PDTS goes high until
0.6
stable CLK output
One Sigma Clock Period Jitter
Configuration Dependent
50
Maximum Absolute Jitter
t_ja
Deviation from Mean.
Configuration Dependent
+200
Pin-to-Pin Skew
Low Skew Outputs
-250
Max. Units
27 MHz
200 MHz
ppm
ppm/V
ns
ns
60
%
10 ms
2
ms
ps
ps
250 ps
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
MDS 275 B
6
Revision 040805
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