ICS95V847 Datasheet, PDF (5/9 Pages) Integrated Circuit Systems – 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)

ICS95V8 47
Timing Requirements
T_A = 0 - 85°C; Supply Voltage A_VDD, V_DD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freq_op
2.5V+0.2V @ 25^oC
45
233
Application Frequency
Range
freq_App
2.5V+0.2V @ 25^oC
95
210
Input clock duty cycle
d_tin
40
60
UNITS
MHz
MHz
%
CLK stabilization
T_STAB
15
µs
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
Low-to high level
propagation delay time
t_PLH1
CLK_IN to any output
High-to low level propagation
delay time
t_PLL1
CLK_IN to any output
Output enable time
Output disable time
t_EN
PD# to any output
tdis
PD# to any output
Period jitter
Half-period jitter
T_{jit (per)}
t(jit_hper)
100MHz to 200MHz
100MHz to 200MHz
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter¹
Phase error
Output to Output Skew
t_sl(i)
t_sl(o)
T_cyc-T_cyc
t_(phase
4
error)
T_skew
100MHz to 200MHz
MIN TYP
5.5
5.5
5
5
-30
-75
1
1
-50
0
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=t_wH/t_c, where
the cycle (t_c) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
MAX UNITS
ns
ns
ns
ns
30
ps
30
ps
4 V/ns
2.5 V/ns
60
ps
50
ps
60
ps
0718D—04/08/05
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