ICS952601 Datasheet, PDF (5/24 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952601
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
V_MID
V_IL
I_IH
I_IL1
I_IL2
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up
resistors
V_IN = 0 V; Inputs with pull-up
resistors
2
1
V_SS - 0.3
-5
-5
-200
V_DD + 0.3 V
1.8
V
0.8
V
5
uA
uA
uA
Operating Supply Current
I_DD3.3OP
Full Active, C_L = Full load;
258
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
29
0.3
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
14.31818
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
C_INX
X1 & X2 pins
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
Modulation Frequency
Triangular Modulation
30
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
Tdrive_PD#
CPU output enable after
PD# de-assertion
Tfall_Pd#
PD# fall time of
Trise_Pd#
PD# rise time of
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
Tfall_CPU_Stop#
PD# fall time of
Trise_CPU_Stop#
PD# rise time of
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
@ I_PULLUP
Current sinking at V_OL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time³
I_PULLUP
T_RI2C
4
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time³
T_FI2C (Min VIH + 0.15) to (Max VIL - 0.15)
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet}
ppm frequency accuracy on PLL outputs.
0701G—10/13/04
350
35
12
7
5
6
5
1.8
33
15
300
5
5
10
5
5
5.5
0.4
1000
300
mA
mA
mA
MHz 3
nH
1
pF
1
pF
1
pF
1
ms 1,2
kHz
1
ns
1
us
1
ns
1
ns
2
us
1
ns
1
ns
2
V
1
V
1
mA
1
ns
1
ns
1
5