ICS951601 Datasheet, PDF (5/9 Pages) Integrated Circuit Systems – General Purpose Frequency Timing Generator

ICS951601
Preliminary Prouct Preview
Byte 1: PCI1A Stop Clocks Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
24
23
20
19
16
15
12
11
PWD
1
1
1
1
1
1
1
1
Description
PCI1A_7
PCI1A_6
PCI1A_5
PCI1A_4
PCI1A_3
PCI1A_2
PCI1A_1
PCI1A_0
Byte 2: PCI2A Stop Clocks
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
35
34
31
29
28
25
-
-
PWD
1
1
1
1
1
1
X
X
Description
PCI2A_2
PCI2A_1
PCI2A_0
PCI1B_2
PCI1B_1
PCI1B_0
Reserved
Reserved
Byte 3: PCI2B Stop Clocks Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
41
40
37
-
-
-
-
-
PWD
1
1
1
X
X
X
X
X
Description
PCI2B_2
PCI2B_1
PCI2B_0
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
48
1
-
-
-
-
-
-
PWD
1
1
X
X
X
X
X
X
Description
48MHz
REF0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 5: Latched Input Read Back Register
(1= enable, 0 = disable)
Bit Pin # PWD
Description
Bit7
-
X SEL2B
Bit6
-
X SEL1B
Bit5
-
X SEL2A
Bit4
-
X SEL1A
Bit3
-
X Reserved
Bit2
-
X Reserved
Bit1
-
X Reserved
Bit0
-
X Reserved
Note: PWD = Power-Up Default
0663B—09/04/03
Byte 6: Reserved for Byte Count Register
(1= enable, 0 = disable)
Bit Pin # PWD
Description
Bit7
-
0
Reserved for read
byte count
Bit6
-
0 Reserved
Bit5
-
0 Reserved
Bit4
-
0 Reserved
Bit3
-
0 Reserved
Bit2
-
1 Reserved
Bit1
-
1 Reserved
Bit0
-
0 Reserved
5