ICS9248-72 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II Systems

ICS9248-72
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit
CPUCLK CPU/2
7 6 54
3V66
1 1 1 1 133.30
66.65
66.65
1 1 1 0 138.01
69.01
69.01
1 1 0 1 142.91
71.45
71.45
1 1 0 0 147.95
73.98
73.98
1 0 1 1 152.49
76.24
76.24
1 0 1 0 156.99
78.49
78.49
Bit
1 0 0 1 162.02
81.01
(7:4)
1 0 0 0 180.00
89.99
81.01
60.00
0 1 1 1 100.23
50.11
66.81
0 1 1 0 105.00
52.49
70.00
0 1 0 1 113.99
56.99
75.66
0 1 0 0 120.00
59.99
80.00
0 0 1 1 128.51
64.25
64.25
0 0 1 0 200.01
100.00
66.66
0 0 0 1 170.03
85.01
56.66
0 0 0 0 66.82
33.40
66.80
Bit3
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 7:4
Bit2
0- Spread spectrum center spread type ±0.25%
1- Spread spectrum down spread type 0 to - 0.5%
Bit1
0- Normal
1- Spread spectrum enable
Bit0
0= Running
1= Tristate all outputs
PCICLK
33.325
34.505
35.725
36.99
38.12
39.245
40.505
30.00
33.405
35
37.83
40.00
32.125
33.33
28.33
33.40
Note1: Default at power-up will be for latched logic inputs to define frequency.
IOAPIC
16.66
17.25
17.86
18.49
19.06
19.62
20.25
15.00
16.70
17.50
18.91
20.00
16.06
16.66
14.16
16.7
PWD
0
XXXX
Note1
0
1
1
0
5